Mitsuru Hiraki

Publication Activity (10 Years)

Years Active: 1995-2023
Publications (10 Years): 4

Top Topics

High Reliability

Industrial Processes

Data Acquisition

Top Venues

Publications

Toyohiro Shimogawa, Makoto Nonaka, Toma Ogata, Toshiki Kiryu, Yasuto Igarashi, Kosuke Yayama, Masahiro Kitamura, Hiromichi Ishikura, Mitsuru Hiraki, Masao Ito, Takashi Kono
An On-Chip DC-DC Converter and Power Management System Achieving Zero Standby-to-Active Transition Time in MCU. A-SSCC (2023)
Fukashi Morishita, Norihito Kato, Satoshi Okubo, Takao Toi, Mitsuru Hiraki, Sugako Otani, Hideaki Abe, Yuji Shinohara, Hiroyuki Kondo
A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera Systems. VLSI Circuits (2021)
Koji Yoichi, Sugako Otani, Kazutoshi Tsuda, Naoya Tokimoto, Hideki Kamegawa, Yoshihisa Satou, Shioto Tanaka, Hideki Otsu, Mitsuru Hiraki, Masao Ito, Mitsuya Fukazawa, Hiroyuki Kondo
A High-Precision Analog Front End Integrated in a 32bit Microcontroller for Industrial Sensing Applications. A-SSCC (2020)
Mitsuru Hiraki, Sugako Otani, Masao Ito, Takuya Mizokami, Masahiro Araki, Hiroyuki Kondo
A Capacitance-to-Digital Converter Integrated in a 32bit Microcontroller for 3D Gesture Sensing. A-SSCC (2018)
Mitsuru Hiraki, K. Fukui, Takayasu Ito
A low-power microcontroller having a 0.5-μA standby current on-chip regulator with dual-reference scheme. IEEE J. Solid State Circuits 39 (4) (2004)
Mitsuru Hiraki, Takayasu Ito, Atsushi Fujiwara, Taichi Ohashi, Tetsuro Hamano, Takaaki Noda
A 63-μW standby power microcontroller with on-chip hybrid regulator scheme. IEEE J. Solid State Circuits 37 (5) (2002)
Mikako Miyama, Shiro Kamohara, Mitsuru Hiraki, Kazunori Onozawa, Hisaaki Kunitomo
Pre-silicon parameter generation methodology using BSIM3 for device/circuit concurrent design. CICC (1999)
Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki
Instruction buffering to reduce power in processors for signal processing. IEEE Trans. Very Large Scale Integr. Syst. 5 (4) (1997)
Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki
Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer. ISLPED (1996)
Mitsuru Hiraki, Hirotsugu Kojima, Hitoshi Misawa, Takashi Akazawa, Yuji Hatano
Data-dependent logic swing internal bus architecture for ultralow-power LSI's. IEEE J. Solid State Circuits 30 (4) (1995)