Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer.
Mitsuru HirakiRaminder Singh BajwaHirotsugu KojimaDouglas J. GornyKen-ichi NittaAvadhani ShridharKatsuro SasakiKoichi SekiPublished in: ISLPED (1996)
Keyphrases
- low power
- high speed
- instruction set
- single chip
- vlsi architecture
- parallel architecture
- power consumption
- low cost
- gate array
- level parallelism
- cmos technology
- memory access
- memory hierarchy
- high power
- nm technology
- floating point
- mixed signal
- low power consumption
- cmos image sensor
- computer architecture
- signal processor
- logic circuits
- clock frequency
- image sensor
- digital signal processing
- vlsi circuits
- hardware implementation
- parallel processing
- wireless transmission
- ultra low power
- real time
- power reduction
- power management
- multithreading
- design considerations
- compressed domain
- application specific
- frame rate
- low complexity
- image processing