A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer.
Norio OhkuboMakoto SuzukiToshinobu ShinboToshiaki YamanakaAkihiro ShimizuKatsuro SasakiYoshinobu NakagomePublished in: IEEE J. Solid State Circuits (1995)
Keyphrases
- high speed
- low power
- circuit design
- power dissipation
- metal oxide semiconductor
- power consumption
- low cost
- analog vlsi
- integrated circuit
- single chip
- floating point
- floating gate
- network simulator
- end to end delay
- vlsi circuits
- delay insensitive
- hardware implementation
- image sensor
- cmos image sensor
- real time
- power supply
- ad hoc networks
- routing protocol
- wireless sensor networks
- focal plane
- cmos technology
- type ii
- interior point methods
- signal processing
- higher throughput
- neural network
- database
- ultra low power