A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits.
Suguru TachibanaHisayuki HiguchiKoichi TakasugiKatsuro SasakiToshiaki YamanakaYoshinobu NakagomePublished in: IEEE J. Solid State Circuits (1995)
Keyphrases
- power consumption
- low power
- power reduction
- cmos technology
- power dissipation
- random access memory
- high speed
- image sensor
- delay insensitive
- end to end delay
- logic circuits
- vlsi circuits
- power saving
- low cost
- mixed signal
- energy efficiency
- flip flops
- power management
- analog vlsi
- low voltage
- single chip
- real time
- data acquisition
- sensor networks
- network simulator
- digital signal processing
- wireless sensor networks
- chip design
- ad hoc networks
- routing protocol
- design considerations
- primal dual
- data transmission
- data flow
- data center
- wide dynamic range