A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators.
Hiroyuki MizunoNozomu MatsuzakiKenichi OsadaToshinobu ShinboNagatoshi OhkiHiroshi IshidaKoichiro IshibashiTokuo KurePublished in: IEEE J. Solid State Circuits (1996)