Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs.
Akira KotabeKiyoo ItohRiichiro TakemuraRyuta TsuchiyaMasashi HoriguchiPublished in: CICC (2011)
Keyphrases
- high speed
- data acquisition
- low power
- real time
- high speed networks
- ultra low power
- low memory
- memory requirements
- frame rate
- computing power
- atomic force microscopy
- random access memory
- read write
- memory size
- memory usage
- limited memory
- focal plane
- main memory
- low cost
- data sets
- memory management
- memory space
- mobile devices
- neural network