A fast motion estimation algorithm and low-power 0.13-um CMOS motion estimation circuits.
Tadayoshi EnomotoAkira KotabePublished in: ISCAS (2) (2001)
Keyphrases
- wireless communication
- low power
- motion estimation
- high speed
- logic circuits
- cmos technology
- delay insensitive
- vlsi circuits
- power reduction
- low cost
- mixed signal
- power consumption
- power dissipation
- wireless transmission
- video coding
- motion compensated
- high power
- image sequences
- motion compensation
- video compression
- video sequences
- power saving
- single chip
- spatial domain
- inter frame
- motion vectors
- low complexity
- digital signal processing
- vlsi architecture
- reference frame
- low power consumption
- optical flow
- computational complexity
- gate array
- block matching
- real time
- coding efficiency
- super resolution
- image sensor
- digital circuits
- multi channel
- macroblock
- rate distortion
- signal processing