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An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture.

Takeshi SakataMasashi HoriguchiTomonori SekiguchiShigeki UedaHitoshi TanakaEiji YamasakiYoshinobu NakagomeMasakazu AokiToru KagaMakoto OhkuraRyo NagaiFumio MuraiToshihiko TanakaShimpei IijimaNatsuki YokoyamaYasushi GotohKen'ichi ShojiTeruaki KisuHisaomi YamashitaTakashi NishidaEiji Takeda
Published in: IEEE J. Solid State Circuits (1995)
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