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Adiabatic SRAM with a Large Margin of VT Variation by Controlling the Cell-power-line and Word-line Voltage.
Shunji Nakata
Takahito Kusumoto
Masayuki Miyama
Yoshio Matsuda
Published in:
ISCAS (2009)
Keyphrases
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low voltage
power line
random access memory
design considerations
leakage current
tree crown
power management
cmos technology
co occurrence
power consumption
novelty detection
n gram
line segments
support vector
power line communication
low cost
low power
cost effective
digital images
data streams