A New Array Architecture for Parallel Testing in VLSI Memories.
Yoshio MatsudaKazutami ArimotoMasaki TsukudeTsukasa OishiKazuyasu FujishimaPublished in: ITC (1989)
Keyphrases
- processor array
- parallel implementation
- parallel algorithm
- mesh connected
- associative memory
- vlsi implementation
- parallel architecture
- level parallelism
- vlsi architecture
- parallel computers
- multi processor
- parallel processing
- parallel programming
- systolic array
- array processor
- single processor
- distributed processing
- parallel computation
- shared memory
- data sets
- real time
- master slave
- design considerations
- computer architecture
- massively parallel
- data flow
- software architecture