Seiji Mochizuki

Publication Activity (10 Years)

Years Active: 2008-2023
Publications (10 Years): 10

Top Topics

Autonomous Driving

Grand Challenge

Real Time Video Processing

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Mai Yamaguchi, Mai Yamakawa, Seiji Mochizuki, Kousuke Imamura, Toshiki Kanamoto, Tetsuya Matsumura
Ultra-Low-Latency Video Coding with Reduced Frame Memory Structure for 4K/8K High-Resolution Video. GCCE (2023)
Yusei Horikawa, Renpei Yoshida, Seiji Mochizuki, Tetsuya Matsumura
Clustering Re-Inference Algorithm for Deep Learning-Based Hierarchical Object Detection System. GCCE (2023)
Yusei Horikawa, Seiji Mochizuki, Kousuke Imamura, Tetsuya Matsumura
CGTI-Net: Deep-Learning-Based Object Detection Network for High-Resolution Aerial Images. IoTaIS (2023)
Katsushige Matsubara, Hanno Lieske, Motoki Kimura, Atsushi Nakamura, Manabu Koike, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei
A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D Control. IEEE J. Solid State Circuits 57 (1) (2022)
Katsushige Matsubara, Hanno Lieske, Motoki Kimura, Atsushi Nakamura, Manabu Koike, Kazuaki Terashima, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei
4.2 A 12nm Autonomous-Driving Processor with 60.4TOPS, 13.8TOPS/W CNN Executed by Task-Separated ASIL D Control. ISSCC (2021)
Kosuke Fukava, Kaito Mori, Kousuke Imamura, Yoshio Matsuda, Tetsuya Matsumura, Seiji Mochizuki
Design and Implementation of Ultra-Low-Latency Video Encoder Using High-Level Synthesis. ISPACS (2019)
Seiji Mochizuki, Kousuke Imamura, Kaito Mori, Yoshio Matsuda, Tetsuya Matsumura
Ultra-low-latency Video Coding Method for Autonomous Vehicles and Virtual Reality Devices. IOTAIS (2018)
Seiji Mochizuki, Katsushige Matsubara, Keisuke Matsumoto, Chi Lan Phuong Nguyen, Tetsuya Shibayama, Kenichi Iwata, Katsuya Mizumoto, Takahiro Irita, Hirotaka Hara, Toshihiro Hattori
A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Chi Lan Phuong Nguyen, My Phi Ngoc Nguyen, Hung Van Cao, Katsushige Matsubara, Keisuke Matsumoto, Seiji Mochizuki, Kenichi Iwata
71% Reducing the memory bandwidth requirement for a multi-standard video codec by lossless compression of video using a combination of 2D-DPCM and Variable Length Coding. ICICDT (2016)
Seiji Mochizuki, Katsushige Matsubara, Keisuke Matsumoto, Chi Lan Phuong Nguyen, Tetsuya Shibayama, Kenichi Iwata, Katsuya Mizumoto, Takahiro Irita, Hirotaka Hara, Toshihiro Hattori
4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems. ISSCC (2016)
Kenichi Iwata, Ryoji Hashimoto, Seiji Mochizuki, Kiyoharu Aizawa
Intra texture prediction based on repetitive pixel replenishment. ICIP (2012)
Tuan Minh Phan Ho, Thang Minh Le, Khanh Duy Vu, Seiji Mochizuki, Kenichi Iwata, Keisuke Matsumoto, Hiroshi Ueda
A 768 Megapixels/sec inverse transform with hybrid architecture for multi-standard decoder. ASICON (2011)
Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori
A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits. IEEE J. Solid State Circuits 45 (1) (2010)
Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa, Toru Fujihira, Kenichi Iwata, Motoki Kimura, Fumitaka Izuhara, Seiji Mochizuki, Masaki Nobori
Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture. ASP-DAC (2009)
Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori
A 342mW mobile application processor with full-HD multi-standard video codec. ISSCC (2009)
Motoki Kimura, Kenichi Iwata, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Hiromi Watanabe
A Full HD Multistandard Video Codec for Mobile Applications. IEEE Micro 29 (6) (2009)
Kenichi Iwata, Seiji Mochizuki, Motoki Kimura, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda, Koji Hosogi, Hiroaki Nakata, Masakazu Ehama, Toru Kengaku, Takuichiro Nakazawa, Hiromi Watanabe
A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS. IEEE J. Solid State Circuits 44 (4) (2009)
Seiji Mochizuki, Tetsuya Shibayama, Masaru Hase, Fumitaka Izuhara, Kazushi Akie, Masaki Nobori, Ren Imaoka, Hiroshi Ueda, Kazuyuki Ishikawa, Hiromi Watanabe
A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS. IEEE J. Solid State Circuits 43 (11) (2008)