A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS.
Kenichi IwataSeiji MochizukiMotoki KimuraTetsuya ShibayamaFumitaka IzuharaHiroshi UedaKoji HosogiHiroaki NakataMasakazu EhamaToru KengakuTakuichiro NakazawaHiromi WatanabePublished in: IEEE J. Solid State Circuits (2009)
Keyphrases
- video coding
- hd video
- high definition
- high profile
- macroblock
- pipeline architecture
- bit rate
- rate distortion
- video codec
- motion estimation
- motion vectors
- video compression
- motion compensated
- motion compensation
- hardware implementation
- video quality
- transform domain
- coding efficiency
- error concealment
- rate control
- bitstream
- error propagation
- compressed video
- mode selection
- bit allocation
- subband
- video coding standard
- compression efficiency
- error resilience
- intra prediction
- mode decision
- video encoder
- video transmission
- low bit rate
- visual quality
- search algorithm
- silicon on insulator
- cmos technology
- distributed video coding
- scalable video coding
- block size
- prediction error
- optical flow
- computational complexity