Tadashi Sumi

Publication Activity (10 Years)

Years Active: 1995-1997
Publications (10 Years): 0

Publications

Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. IEEE J. Solid State Circuits 32 (2) (1997)
Kazuya Yamanaka, Sumitaka Takeuchi, Shuji Murakami, Masayuki Koyama, Jun Ido, Takashi Fujiwara, Susumu Hirano, Keisuke Okada, Tadashi Sumi
A multilevel QAM demodulator VLSI with wideband carrier recovery and dual equalizing mode. IEEE J. Solid State Circuits 32 (7) (1997)
Hiroshi Makino, Hiroaki Suzuki, Hiroyuki Morinaka, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
A 286 MHz 64-b floating point multiplier with enhanced CG operation. IEEE J. Solid State Circuits 31 (4) (1996)
Hisayasu Sato, Kenichi Kashiwagi, Kazuhito Niwano, Tetsuya Iga, Tatsuhiko Ikeda, Koichiro Mashiko, Tadashi Sumi, Koji Tsuchihashi
A 1.9-GHz single chip IF transceiver for digital cordless phones. IEEE J. Solid State Circuits 31 (12) (1996)
Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
Leading-zero anticipatory logic for high-speed floating point addition. IEEE J. Solid State Circuits 31 (8) (1996)
Tsutomu Yoshimura, Harufusa Kondoh, Yoshio Matsuda, Tadashi Sumi
A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication. IEEE J. Solid State Circuits 31 (7) (1996)
Kazuya Ishihara, Shinichi Masuda, Shin-ichi Hattori, Hirofumi Nishikawa, Yoshihide Ajioka, Tsuyoshi Yamada, Hiroyuki Amishiro, Shin-ichi Uramoto, Masahiko Yoshimoto, Tadashi Sumi
A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search. IEEE J. Solid State Circuits 30 (12) (1995)