Hiroaki Suzuki

Publication Activity (10 Years)

Years Active: 1995-2023
Publications (10 Years): 11

Top Topics

Polynomial Time Complexity

Pspace Complete

Top Venues

J. Inf. Process.

Publications

Taichi Kokubu, Tatsuya Hikida, Hiroaki Suzuki
Patterning-Based Self-Assembly of Specific and Functional Structures. J. Robotics Mechatronics 35 (5) (2023)
Kanji Kaneko, Mamiko Tsugane, Yosuke Hasegawa, Takeshi Hayakawa, Hiroaki Suzuki
Experimental and Numerical Investigation of Particle Capture for Agglutination-Based NP detection Using the Vibration-Induced Flow. MHS (2023)
Kanji Kaneko, Mamiko Tsugane, Taku Sato, Takeshi Hayakawa, Yosuke Hasegawa, Hiroaki Suzuki
Detection of nanoparticles in a minute sample using the vibration induced flow. NEMS (2022)
Hiroaki Suzuki, Wataru Takahashi, Kazutoshi Wakabayashi, Hideharu Amano
A programming environment for multi-FPGA systems based on CyberWorkBench: an integrated design tool. HEART (2021)
Toshiyuki Matsui, Hiroaki Suzuki, Takeshi Hayakawa
DESIGN AND EVALUATION OF MICROMIXIER WITH LOW DEAD VOLUME BASED ON VIBRATION-INDUCED FLOW. MHS (2019)
Hiroaki Suzuki, Daiki Chiba, Yoshiro Yoneya, Tatsuya Mori, Shigeki Goto
ShamFinder: An Automated Framework for Detecting IDN Homographs. Internet Measurement Conference (2019)
Hiroaki Suzuki, Daiki Chiba, Yoshiro Yoneya, Tatsuya Mori, Shigeki Goto
ShamFinder: An Automated Framework for Detecting IDN Homographs. CoRR (2019)
S. Katsuta, T. Okano, Hiroaki Suzuki
Reagent Handling and Delivery System Using Cell-Sized Liposomes. NEMS (2018)
Akihiro Uejima, Hiroaki Suzuki, Atsuki Okada
The Complexity of Generalized Pipe Link Puzzles. J. Inf. Process. 25 (2017)
Hiromitsu Miyata, Hiroaki Suzuki
Do Subliminal Hints Facilitate Sequential Planning When Solving a Spatial Insight Problem? CogSci (2016)
Yoshitaka Yoshizumi, Masatoshi Yokokawa, Hiroaki Suzuki
Self-deformable micro/nanomotors with organic-inorganic hybrid structures. NEMS (2016)
Akihiro Uejima, Hiroaki Suzuki
Fillmat is NP-Complete and ASP-Complete. J. Inf. Process. 23 (3) (2015)
Hiroaki Suzuki, Haruaki Fukuda, Hiromitsu Miyata, Keishi Tsuchiya
Exploring the Unconscious Nature of Insight Using Continuous Flash Suppression and a Dual Task. CogSci (2014)
Natsumi Kawai, Shinichi Takayama, Junya Masumi, Naoto Kikuchi, Yasuo Itoh, Kyosuke Ogawa, Akimitsu Ugawa, Hiroaki Suzuki, Yasunori Tanaka
A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving. IEEE J. Solid State Circuits 49 (11) (2014)
Satoshi V. Suzuki, Hiroaki Suzuki
Improving Academic Essays by Writing and Reading Peer Annotations on Source Documents. CSCL (2) (2013)
Ryota Henmi, Yusuke Nishimura, Hiroaki Suzuki, Shinji Fukuma, Shin-ichiro Mori, Akinori Yamaguchi, Shinji Tomita
Prototype Implementation of a GPU-based Interactive Coupled Fluid-Structure Simulation. SNPD (2012)
Haruaki Fukuda, Hiroaki Suzuki, Ayumi Yamada
Automatic facilitation of social behavior by implicit inferring of social intention. CogSci (2012)
Tatsuya Osaki, Takahiro Kakegawa, Hiroaki Suzuki, Junji Fukuda
Electrical detachment of cells for engineering capillary-like structures in a photocrosslinkable hydrogel. EMBC (2011)
Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara
Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling. ACM Trans. Design Autom. Electr. Syst. 15 (2) (2010)
Hirotoshi Asano, Hiroaki Suzuki, Masafumi Uchida, Hideto Ide
Basic examination concerning multiagent cooperation with entrainment. Artif. Life Robotics 14 (1) (2009)
Satoshi V. Suzuki, Aiko Shiraishi, Hiroaki Suzuki
Eliciting Emotional Thought During Critical Reading for Academic Writing. AIED (2009)
Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara
Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling. DAC (2008)
Hiroaki Suzuki, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara
Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology. ISLPED (2008)
Masako Fujii, Hiroaki Suzuki, Hiromi Notani, Hiroshi Makino, Hirofumi Shinohara
On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect. ESSCIRC (2008)
Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy
Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders. IEICE Trans. Electron. (4) (2007)
Hiroaki Suzuki, Chris H. Kim, Kaushik Roy
Fast Tag Comparator Using Diode Partitioned Domino for 64-bit Microprocessors. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2007)
Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy
Low-power carry-select adder using adaptive supply voltage based on input vector patterns. ISLPED (2004)
Tadashi Dohi, Hiroaki Suzuki, Kishor S. Trivedi
Comparing Software Rejuvenation Policies under Different Dependability Measures. IEICE Trans. Inf. Syst. (8) (2004)
Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy
Low Power Adder with Adaptive Supply Voltage. ICCD (2003)
Hiroaki Suzuki, Tadashi Dohi, Hiroyuki Okamura
Cost-Effective Analysis of Software Systems with Periodic Rejuvenation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Hiroaki Suzuki, Hiroshi Making, Yoshio Matsuda
Novel VLIW code compaction method for a 3D geometry processor. CICC (2000)
Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. IEEE J. Solid State Circuits 32 (2) (1997)
Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko
Authors Reply. IEEE J. Solid State Circuits 32 (2) (1997)
Hiroaki Suzuki, Hiroshi Makino, Koichiro Mashiko, Hisanori Hamano
A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme. ICCD (1997)
Kiniio Ueda, Hiroaki Suzuki, Kakutaro Suda, Hirofumi Shinohara, Koichiro Mashiko
A 64-bit carry look ahead adder using pass transistor BiCMOS gates. IEEE J. Solid State Circuits 31 (6) (1996)
Hiroshi Makino, Hiroaki Suzuki, Hiroyuki Morinaka, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
A 286 MHz 64-b floating point multiplier with enhanced CG operation. IEEE J. Solid State Circuits 31 (4) (1996)
Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko
An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. IEEE J. Solid State Circuits 31 (6) (1996)
Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
Leading-zero anticipatory logic for high-speed floating point addition. IEEE J. Solid State Circuits 31 (8) (1996)
Yasunobu Nakase, Hiroaki Suzuki, Hiroshi Makino, Hirofumi Shinohara, Koichiro Mashiko
A BiCMOS wired-OR logic. IEEE J. Solid State Circuits 30 (6) (1995)