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An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture.
Hiroshi Makino
Yasunobu Nakase
Hiroaki Suzuki
Hiroyuki Morinaka
Hirofumi Shinohara
Koichiro Mashiko
Published in:
IEEE J. Solid State Circuits (1996)
Keyphrases
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high speed
real time
hardware implementation
gray code
software architecture
low power
management system
logical operations
neural network
data sets
frame rate
network architecture
network simulator
shift register
bit string
analog to digital converter