On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect.
Masako FujiiHiroaki SuzukiHiromi NotaniHiroshi MakinoHirofumi ShinoharaPublished in: ESSCIRC (2008)
Keyphrases
- low voltage
- leakage current
- cmos technology
- high speed
- circuit design
- analog vlsi
- short circuit
- duty cycle
- power consumption
- evolvable hardware
- power dissipation
- single phase
- low power
- nm technology
- dynamic programming
- real time
- analog circuits
- optimal solution
- parallel processing
- electronic circuits
- power management
- micron cmos
- operating point
- digital circuits
- control method
- human body
- neural network