A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme.

Hiroaki Suzuki Hiroshi Makino Koichiro Mashiko Hisanori Hamano

Published in: ICCD (1997)

Keyphrases

floating point
sparse matrices
high speed
square root
fixed point
delay insensitive
asynchronous circuits
fast fourier transform
high level synthesis
floating point arithmetic
instruction set
power consumption
reinforcement learning
pairwise
signal processing
sufficient conditions