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Leading-zero anticipatory logic for high-speed floating point addition.

Hiroaki SuzukiHiroyuki MorinakaHiroshi MakinoYasunobu NakaseKoichiro MashikoTadashi Sumi
Published in: IEEE J. Solid State Circuits (1996)
Keyphrases
  • floating point
  • high speed
  • fixed point
  • square root
  • instruction set
  • sparse matrices
  • floating point arithmetic
  • computer vision
  • real time
  • multi view
  • modal logic
  • low power
  • interval arithmetic