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Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit.
Shunji Nakata
Hirotsugu Suzuki
Ryota Honda
Takahito Kusumoto
Shin'ichiro Mutoh
Hiroshi Makino
Masayuki Miyama
Yoshio Matsuda
Published in:
ISCAS (2010)
Keyphrases
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low voltage
duty cycle
power consumption
high speed
access control
short circuit
random access memory
power reduction
shared information
line segments
random access
power system
cmos technology
analog circuits
single phase
electronic circuits
data transmission
low power
real time