Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs.
Kazuhiko TeradaHiroyuki UzawaNamiko IkedaSatoshi ShigematsuNobuyuki TanakaMasami UranoPublished in: FPL (2012)
Keyphrases
- hw sw
- hardware software
- embedded systems
- hardware software partitioning
- hardware software co design
- hardware and software
- design methodology
- field programmable gate array
- design issues
- general purpose
- model checking
- evolutionary computation
- data processing
- information systems
- hardware implementation
- hardware design
- genetic programming
- low cost
- query processing