Area efficient, high speed parallel counter circuits using charge recycling threshold logic.

Peter Celinski Derek Abbott Sorin Dan Cotofana

Published in: ISCAS (5) (2003)

Keyphrases

high speed
low power
parallel execution
logic synthesis
shift register
real time
computationally efficient
delay insensitive
database
genetic algorithm
logic programming
parallel processing
parallel architectures
predicate logic
logic circuits