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An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set 2n+1, 2n, 2n-1.
Kazeem Alagbe Gbolagade
George Razvan Voicu
Sorin Dan Cotofana
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2011)
Keyphrases
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small number
hardware design
low cost
relational databases
evolutionary algorithm
hardware implementation
binary representation