Somayeh Timarchi

Publication Activity (10 Years)

Years Active: 2005-2023
Publications (10 Years): 17

Top Topics

Low Power Consumption

Rademacher Complexity

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Circuits Syst. Signal Process.

IEEE Trans. Circuits Syst. II Express Briefs

Microprocess. Microsystems

Publications

Mohammad Mehdi Gilanian Sadeghi, Somayeh Timarchi, Mahmood Fazlali
High-Performance Memory Allocation on FPGA With Reduced Internal Fragmentation. IEEE Access 11 (2023)
Ladan Sayadi, Somayeh Timarchi, Akbar Sheikh-Akbari
Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4:2 Compressors. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (4) (2023)
Mina Raouf, Somayeh Timarchi
Non-Volatile and High-Performance Cascadable Spintronic Full-Adder With No Sensitivity to Input Scheduling. IEEE Trans. Circuits Syst. II Express Briefs 70 (6) (2023)
Yahya Arzani Birgani, Somayeh Timarchi, Ayesha Khalid
Ultra-lightweight FPGA-based RC5 designs via data-dependent rotation block optimization. Microprocess. Microsystems 93 (2022)
Yahya Arzani Birgani, Somayeh Timarchi, Ayesha Khalid
Area-Time-Efficient Scalable Schoolbook Polynomial Multiplier for Lattice-Based Cryptography. IEEE Trans. Circuits Syst. II Express Briefs 69 (12) (2022)
Seyed Amir Hossein Ejtahed, Somayeh Timarchi
Efficient Approximate Multiplier Based on a New 1-Gate Approximate Compressor. Circuits Syst. Signal Process. 41 (5) (2022)
Ahmad Shabani, Mohammad Sabri, Bahareh Khabbazan, Somayeh Timarchi
Area and Power-Efficient Variable-Sized DCT Architecture for HEVC Using Muxed-MCM Problem. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (3) (2021)
Hossein Mahdavi, Somayeh Timarchi
Improving Architectures of Binary Signed-Digit CORDIC With Generic/Specific Initial Angles. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2020)
Adib Armand, Somayeh Timarchi, Hossein Mahdavi
Optimized Parity-Based Error Detection and Correction Methods for Residue Number System. J. Circuits Syst. Comput. 28 (1) (2019)
Somayeh Timarchi, Negar Akbarzadeh
- 1 Adder and Multiplier. Circuits Syst. Signal Process. 38 (5) (2019)
Ahmad Shabani, Somayeh Timarchi, Hossein Mahdavi
Power and area efficient CORDIC-Based DCT using direct realization of decomposed matrix. Microelectron. J. 91 (2019)
Hossein Mahdavi, Somayeh Timarchi
Area-Time-Power Efficient FFT Architectures Based on Binary-Signed-Digit CORDIC. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2019)
Hamed Naseri, Somayeh Timarchi
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates. IEEE Trans. Very Large Scale Integr. Syst. 26 (8) (2018)
Ahmad Shabani, Somayeh Timarchi
Low-power DCT-based compressor for wireless capsule endoscopy. Signal Process. Image Commun. 59 (2017)
Somayeh Timarchi, Massimo Alioto
Ultra-low voltage standard cell libraries: Design strategies and a case study. ICECS (2016)
Masoud Abbasi Alaie, Somayeh Timarchi
+1 multiplier. Int. J. Comput. Aided Eng. Technol. 8 (3) (2016)
Majid Moghaddam, Somayeh Timarchi, Mohammad Hossein Moaiyeri, Mohammad Eshghi
An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques. Circuits Syst. Signal Process. 35 (5) (2016)
Mahmood Fazlali, Hadi Valikhani, Somayeh Timarchi, Hadi Tabatabaee Malazi
Fast architecture for decimal digit multiplication. Microprocess. Microsystems 39 (4-5) (2015)
Ardalan Najafi, Somayeh Timarchi, Amir Najafi
High-speed energy-efficient 5: 2 compressor. MIPRO (2014)
Somayeh Timarchi, Maryam Saremi, Mahmood Fazlali, Georgi Gaydadjiev
High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding. VLSI-SoC (2013)
Somayeh Timarchi, Mahmood Fazlali
+ 1}. IET Comput. Digit. Tech. 6 (5) (2012)
Amir Sabbagh Molahosseini, Keivan Navi, Chitra Dadkhah, Omid Kavehei, Somayeh Timarchi
+1 Based on New CRTs. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2010)
Somayeh Timarchi, Mahmood Fazlali, Sorin Dan Cotofana
+1} based on a novel RNS representation. ICCD (2010)
Somayeh Timarchi, Keivan Navi
A new algorithm for determining all possible symmetric hybrid redundant numbers. IEICE Electron. Express 6 (1) (2009)
Keivan Navi, Mehrdad Maeen, Vahid Foroutan, Somayeh Timarchi, Omid Kavehei
A novel low-power full-adder cell for low voltage. Integr. 42 (4) (2009)
Somayeh Timarchi, Keivan Navi
Arithmetic Circuits of Redundant SUT-RNS. IEEE Trans. Instrum. Meas. 58 (9) (2009)
Somayeh Timarchi, Keivan Navi, Omid Kavehei
Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation. ISVLSI (2009)
Somayeh Timarchi, Seyed Ghassem Miremadi, Ali Reza Ejlali
Evaluation of Some Exponential Random Number Generators Implemented by FPGA. Parallel and Distributed Computing and Networks (2005)