Roman L. Lysecky

Publication Activity (10 Years)

Years Active: 1999-2016
Publications (10 Years): 1

Top Topics

Dynamic Optimization

Review Questions

Computing Power

Top Venues

ACM Trans. Design Autom. Electr. Syst.

ACM Trans. Embed. Comput. Syst.

Publications

Adrian Lizarraga, Roman L. Lysecky, Jonathan Sprinkle
Model-Driven Optimization of Data-Adaptable Embedded Systems. COMPSAC (2016)
Lu Ding, Adrian Lizarraga, Ashish Shenoy, Ann Gordon-Ross, Susan Lysecky, Roman L. Lysecky
Application-Specific Customization of Dynamic Profiling Mechanisms for Sensor Networks. IEEE Access 3 (2015)
Jong Chul Lee, Roman L. Lysecky
System-Level Observation Framework for Non-Intrusive Runtime Monitoring of Embedded Systems. ACM Trans. Design Autom. Electr. Syst. 20 (3) (2015)
Alex D. Edgcomb, Frank Vahid, Roman L. Lysecky
Students learn more with less text that covers the same core topics. FIE (2015)
Johannes Sametinger, Jerzy W. Rozenblit, Roman L. Lysecky, Peter Ott
Security challenges for medical devices. Commun. ACM 58 (4) (2015)
Jin Sun, Roman L. Lysecky, Karthik Shankar, Avinash Karanth Kodi, Ahmed Louri, Janet Roveda
Workload assignment considering NBTI degradation in multicore systems. ACM J. Emerg. Technol. Comput. Syst. 10 (1) (2014)
Jingqing Mu, Karthik Shankar, Roman L. Lysecky
Profiling and online system-level performance and power estimation for dynamically adaptable embedded systems. ACM Trans. Embed. Comput. Syst. 12 (3) (2013)
Nathan Sandoval, Casey Mackin, Sean Whitsitt, Roman L. Lysecky, Jonathan Sprinkle
Runtime hardware/software task transition scheduling for data-adaptable embedded systems. FPT (2013)
Nathan Sandoval, Casey Mackin, Sean Whitsitt, Roman L. Lysecky, Jonathan Sprinkle
System Throughput Optimization and Runtime Communication Middleware Supporting Dynamic Software-Hardware Task Migration in Data Adaptable Embedded Systems. ECBS (2013)
Nathan Sandoval, Casey Mackin, Roman L. Lysecky, Jonathan Sprinkle
How You Can Learn to Stop Worrying and Love Reconfigurable Embedded Systems: A Tutorial. ECBS (2013)
Jingqing Mu, Roman L. Lysecky
Adaptive online heuristic performance estimation and power optimization for reconfigurable embedded systems. CODES+ISSS (2012)
Arslan Munir, Ann Gordon-Ross, Susan Lysecky, Roman L. Lysecky
Online algorithms for wireless sensor networks dynamic optimization. CCNC (2012)
Sean Whitsitt, Jonathan Sprinkle, Roman L. Lysecky
An overseer control methodology for data adaptable embedded systems. MPM@MoDELS (2012)
Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman L. Lysecky, Karthik Shankar, Janet Meiling Wang Roveda
A self-tuning design methodology for power-efficient multi-core systems. ACM Trans. Design Autom. Electr. Syst. 18 (1) (2012)
Andrew Milakovich, Vijay Shankar Gopinath, Roman L. Lysecky, Jonathan Sprinkle
Automated Software Generation and Hardware Coprocessor Synthesis for Data-Adaptable Reconfigurable Systems. ECBS (2012)
Jingqing Mu, Roman L. Lysecky
Profile assisted online system-level performance and power estimation for dynamic reconfigurable embedded systems. ASP-DAC (2011)
Vijay Shankar Gopinath, Jonathan Sprinkle, Roman L. Lysecky
Modeling of Data Adaptable Reconfigurable Embedded Systems. ECBS (2011)
Sachidanand Mahadevan, Vijay Shankar Gopinath, Roman L. Lysecky, Jonathan Sprinkle, Jerzy W. Rozenblit, Michael W. Marcellin
Hardware/Software Communication Middleware for Data Adaptable Embedded Systems. ECBS (2011)
Ajay Nair, Karthik Shankar, Roman L. Lysecky
Efficient hardware-based nonintrusive dynamic application profiling. ACM Trans. Embed. Comput. Syst. 10 (3) (2011)
Rahul Kalra, Roman L. Lysecky
Configuration Locking and Schedulability Estimation for Reduced Reconfiguration Overheads of Reconfigurable Systems. IEEE Trans. Very Large Scale Integr. Syst. 18 (4) (2010)
Karthik Shankar, Roman L. Lysecky
Control Focused Soft Error Detection for Embedded Applications. IEEE Embed. Syst. Lett. 2 (4) (2010)
Jin Sun, Roman L. Lysecky, Karthik Shankar, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang
Workload capacity considering NBTI degradation in multi-core systems. ASP-DAC (2010)
Arslan Munir, Ann Gordon-Ross, Susan Lysecky, Roman L. Lysecky
A lightweight dynamic optimization methodology for wireless sensor networks. WiMob (2010)
Jeff Hiner, Ashish Shenoy, Roman L. Lysecky, Susan Lysecky, Ann Gordon-Ross
Transaction-Level Modeling for Sensor Networks Using SystemC. SUTC/UMC (2010)
Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman L. Lysecky, Karthik Shankar, Janet Meiling Wang Roveda
A self-evolving design methodology for power efficient multi-core systems. ICCAD (2010)
Ashish Shenoy, Jeff Hiner, Susan Lysecky, Roman L. Lysecky, Ann Gordon-Ross
Evaluation of Dynamic Profiling Methodologies for Optimization of Sensor Networks. IEEE Embed. Syst. Lett. 2 (1) (2010)
Karthik Shankar, Roman L. Lysecky
Non-intrusive dynamic application profiling for multitasked applications. DAC (2009)
Lance Saldanha, Roman L. Lysecky
Float-to-fixed and fixed-to-float hardware converters for rapid hardware/software partitioning of floating point software applications to static and dynamic fixed point coprocessors. Des. Autom. Embed. Syst. 13 (3) (2009)
Roman L. Lysecky, Frank Vahid
Design and implementation of a MicroBlaze-based warp processor. ACM Trans. Embed. Comput. Syst. 8 (3) (2009)
Jingqing Mu, Roman L. Lysecky
Autonomous hardware/software partitioning and voltage/frequency scaling for low-power embedded systems. ACM Trans. Design Autom. Electr. Syst. 15 (1) (2009)
Ajay Nair, Roman L. Lysecky
Non-intrusive dynamic application profiler for detailed loop execution characterization. CASES (2008)
Frank Vahid, Greg Stitt, Roman L. Lysecky
Warp Processing: Dynamic Translation of Binaries to FPGA Circuits. Computer 41 (7) (2008)
Mark Hammerquist, Roman L. Lysecky
Design space exploration for application specific FPGAS in system-on-a-chip designs. SoCC (2008)
Lance Saldanha, Roman L. Lysecky
Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits. CODES+ISSS (2008)
Roman L. Lysecky
Scalability and Parallel Execution of Warp Processing: Dynamic Hardware/Software Partitioning. Int. J. Parallel Program. 36 (5) (2008)
Roman L. Lysecky
Low-power warp processor for power efficient high-performance embedded systems. DATE (2007)
Roman L. Lysecky, Frank Vahid
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning CoRR (2007)
David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen
Application-specific customization of parameterized FPGA soft-core processors. ICCAD (2006)
Roman L. Lysecky, Greg Stitt, Frank Vahid
Warp Processors. ACM Trans. Design Autom. Electr. Syst. 11 (3) (2006)
David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky
Conjoining soft-core FPGA processors. ICCAD (2006)
Roman L. Lysecky, Kris Miller, Frank Vahid, Kees A. Vissers
Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only). FPGA (2005)
Roman L. Lysecky, Frank Vahid
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. DATE (2005)
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. FCCM (2005)
Roman L. Lysecky, Susan Cotterell, Frank Vahid
A fast on-chip profiler memory using a pipelined binary tree. IEEE Trans. Very Large Scale Integr. Syst. 12 (1) (2004)
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
Dynamic FPGA routing for just-in-time FPGA compilation. DAC (2004)
Roman L. Lysecky, Frank Vahid
A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. DATE (2004)
Chuanjun Zhang, Frank Vahid, Roman L. Lysecky
A Self-Tuning Cache Architecture for Embedded Systems. DATE (2004)
Chuanjun Zhang, Frank Vahid, Roman L. Lysecky
A self-tuning cache architecture for embedded systems. ACM Trans. Embed. Comput. Syst. 3 (2) (2004)
Roman L. Lysecky, Frank Vahid
A codesigned on-chip logic minimizer. CODES+ISSS (2003)
Frank Vahid, Roman L. Lysecky, Chuanjun Zhang, Greg Stitt
Highly configurable platforms for embedded computing systems. Microelectron. J. 34 (11) (2003)
Roman L. Lysecky, Frank Vahid
On-chip logic minimization. DAC (2003)
Greg Stitt, Roman L. Lysecky, Frank Vahid
Dynamic hardware/software partitioning: a first approach. DAC (2003)
Roman L. Lysecky, Frank Vahid
Prefetching for improved bus wrapper performance in cores. ACM Trans. Design Autom. Electr. Syst. 7 (1) (2002)
Roman L. Lysecky, Susan Cotterell, Frank Vahid
A fast on-chip profiler memory. DAC (2002)
Roman L. Lysecky, Frank Vahid, Tony Givargis
Techniques for Reducing Read Latency of Core Bus Wrappers. DATE (2000)
Roman L. Lysecky, Frank Vahid, Tony Givargis
Experiments with the Peripheral Virtual Component Interface. ISSS (2000)
Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky
A first-step towards an architecture tuning methodology for low power. CASES (2000)
Roman L. Lysecky, Frank Vahid, Rilesh Patel, Tony Givargis
Pre-Fetching for Improved Core Interfacing. ISSS (1999)