Juanjo Noguera

Publication Activity (10 Years)

Years Active: 1999-2019
Publications (10 Years): 2

Top Topics

Artificial Intelligent

Ai Technologies

Hardware Software Co Design

Top Venues

Hot Chips Symposium

Publications

Sagheer Ahmad, Sridhar Subramanian, Vamsi Boppana, Shankar Lakka, Fu-Hing Ho, Tomai Knopp, Juanjo Noguera, Gaurav Singh, Ralph Wittig
Xilinx First 7nm Device: Versal AI Core (VC1902). Hot Chips Symposium (2019)
Daniel Jiménez-González, Carlos Álvarez, Antonio Filgueras, Xavier Martorell, Jan Langer, Juanjo Noguera, Kees A. Vissers
Coarse-Grain Performance Estimator for Heterogeneous Parallel Computing Architectures like Zynq All-Programmable SoC. CoRR (2015)
Antonio Filgueras, Eduard Gil, Daniel Jiménez-González, Carlos Álvarez, Xavier Martorell, Jan Langer, Juanjo Noguera, Kees A. Vissers
OmpSs@Zynq all-programmable SoC ecosystem. FPGA (2014)
Antonio Filgueras, Eduard Gil, Carlos Álvarez, Daniel Jiménez-González, Xavier Martorell, Jan Langer, Juanjo Noguera
Heterogeneous tasking on SMP/FPGA SoCs: The case of OmpSs and the Zynq. VLSI-SoC (2013)
Baris Özgül, Jan Langer, Juanjo Noguera, Kees A. Vissers
Software-programmable digital pre-distortion on the Zynq SoC. VLSI-SoC (2013)
Kees A. Vissers, Stephen Neuendorffer, Juanjo Noguera
Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools. DATE (2011)
Joachim Meyer, Juanjo Noguera, Michael Hübner, Rodney Stewart, Jürgen Becker
Embedded Systems Start-Up under Timing Constraints on Modern FPGAs. FPL (2011)
Jorg Lotze, Suhaib A. Fahmy, Juanjo Noguera, Linda Doyle
A Model-Based Approach to Cognitive Radio Design. IEEE J. Sel. Areas Commun. 29 (2) (2011)
Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees A. Vissers, Zhiru Zhang
High-Level Synthesis for FPGAs: From Prototyping to Deployment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (4) (2011)
Joachim Meyer, Juanjo Noguera, Michael Hübner, Lars Braun, Oliver Sander, R. M. Gil, Rodney Stewart, Jürgen Becker
Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration. DATE (2011)
Michael Hübner, Diana Göhringer, Juanjo Noguera, Jürgen Becker
Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs. IPDPS Workshops (2010)
Paul D. Sutton, Jörg Lotze, Hicham Lahlou, Baris Özgül, Suhaib A. Fahmy, Keith E. Nolan, Juanjo Noguera, Linda E. Doyle
Multi-platform demonstrations using the Iris architecture for cognitive radio network testbeds. CrownCom (2010)
Paul D. Sutton, Jörg Lotze, Hicham Lahlou, Suhaib A. Fahmy, Keith E. Nolan, Baris Özgül, Thomas W. Rondeau, Juanjo Noguera, Linda Doyle
Iris: an architecture for cognitive radio networking testbeds. IEEE Commun. Mag. 48 (9) (2010)
Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil D. Dutt
Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures. ACM Trans. Reconfigurable Technol. Syst. 3 (3) (2010)
Michael Hübner, Joachim Meyer, Oliver Sander, Lars Braun, Jürgen Becker, Juanjo Noguera, Rodney Stewart
Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration. ISVLSI (2010)
Joachim Meyer, Michael Hübner, Lars Braun, Oliver Sander, Juanjo Noguera, Rodney Stewart, Jürgen Becker
FPGA Startup Through Sequential Partial and Dynamic Reconfiguration. ISVLSI (Selected papers) (2010)
Suhaib A. Fahmy, Jorg Lotze, Juanjo Noguera, Linda Doyle, Robert Esser
Generic Software Framework for Adaptive Applications on FPGAs. FCCM (2009)
Jorg Lotze, Suhaib A. Fahmy, Juanjo Noguera, Baris Özgül, Linda Doyle, Robert Esser
Development Framework for Implementing FPGA-Based Cognitive Network Nodes. GLOBECOM (2009)
Juanjo Noguera, Robert Esser, Katarina Paulsson, Michael Hübner, Jürgen Becker
Towards Novel Approaches in Design Automation for FPGA Power Optimization. PATMOS (2008)
Juanjo Noguera, Irwin O. Kennedy
Power Reduction in Network Equipment through Adaptive Partial Reconfiguration. FPL (2007)
Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt, Juanjo Noguera
Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures. DAC (2007)
Juanjo Noguera, Luis Baldez, Narcis Simon, Lluis Abello
Software-friendly HW/SW co-simulation: an industrial case study. DATE Designers' Forum (2006)
Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil D. Dutt
Minimizing peak power for application chains on architectures with partial dynamic reconfiguration. FPT (2006)
Juanjo Noguera, Rosa M. Badia
System-level power-performance tradeoffs for reconfigurable computing. IEEE Trans. Very Large Scale Integr. Syst. 14 (7) (2006)
Juanjo Noguera, Rosa M. Badia
Performance and Energy Analysis of Task-Level Graph Transformation Techniques for Dynamically Reconfigurable Architectures. FPL (2005)
Zexin Pan, Juanjo Noguera, B. Earl Wells
Improved Microarchitecture Support for Dynamic Task Scheduling on Reconfigurable Architectures. ERSA (2005)
Juanjo Noguera, Rosa M. Badia
Power-performance trade-offs for reconfigurable computing. CODES+ISSS (2004)
Juanjo Noguera, Rosa M. Badia
Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling. ACM Trans. Embed. Comput. Syst. 3 (2) (2004)
Juanjo Noguera, Rosa M. Badia
System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures. CASES (2003)
Juanjo Noguera, Rosa M. Badia
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures. CODES (2002)
Juanjo Noguera, Rosa M. Badia
HW/SW codesign techniques for dynamically reconfigurable architectures. IEEE Trans. Very Large Scale Integr. Syst. 10 (4) (2002)
Juanjo Noguera, Rosa M. Badia
A HW/SW partitioning algorithm for dynamically reconfigurable architectures. DATE (2001)
Juanjo Noguera, Rosa M. Badia
Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers. FPL (2000)
Josep Solé-Pareta, Davide Careglio, Salvatore Spadaro, Jaume Masip-Torné, Juanjo Noguera, Gabriel Junyent
Modelling and Performance Evaluation of a National Scale Switchless Based Network. INTERWORKING (2000)
Juanjo Noguera, Rosa M. Badia
Run-Time HW/SW Codesign for Discrete Event Systems using Dynamically Reconfigurable Architectures. ISSS (2000)
Juanjo Noguera, Rosa M. Badia, Jordi Domingo-Pascual, Josep Solé-Pareta
Reconfigurable Computing: An Innovative Solution for Multimedia and Telecommunication Networks Simulation. EUROMICRO (1999)
Juanjo Noguera, Rosa M. Badia, Jordi Domingo-Pascual, Josep Solé-Pareta
A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation. FPL (1999)