Login / Signup
Jichun Bu
Publication Activity (10 Years)
Years Active: 1987-2013
Publications (10 Years): 0
Top Topics
Hybrid Learning
Fine Grain
Systolic Array
Parallel Genetic Algorithm
Top Venues
HPCC/EUC
ASICON
</>
Publications
</>
Xiang Wang
,
Su Zhang
,
Wei Ni
,
Yukun Song
,
Yanhui Yang
,
Jichun Bu
Design of a hybrid reconfigurable coprocessor.
ASICON
(2013)
Wei Ni
,
Xiang Wang
,
Su Zhang
,
Yukun Song
,
Yanhui Yang
,
Jichun Bu
A Hybrid Reconfigurable System for Parallel and Intensive Computation.
HPCC/EUC
(2013)
Ed F. Deprettere
,
Gerben J. Hekstra
,
Li-Sheng Shen
,
Jichun Bu
,
Gerrit Boersma
A parallel system for photo realistic artificial scene rendering.
ASAP
(1994)
Jichun Bu
,
Ed F. Deprettere
Processor clustering for the design of optimal fixed-size systolic arrays.
ASAP
(1991)
Jichun Bu
,
Ed F. Deprettere
,
Lothar Thiele
Systolic array implementation of nested loop programs.
ASAP
(1990)
Alfons A. J. de Lange
,
Ed F. Deprettere
,
Alle-Jan van der Veen
,
Jichun Bu
Real time application of the floating point pipeline CORDIC processor in massive-parallel pipelined DSP algorithms.
ICASSP
(1990)
Jichun Bu
,
Ed F. Deprettere
,
Patrick M. Dewilde
A design methodology for fixed-size systolic arrays.
ASAP
(1990)
Jichun Bu
,
Ed F. Deprettere
A VLSI system architecture for high-speed radiative transfer 3D image synthesis.
Vis. Comput.
5 (3) (1989)
Jichun Bu
,
Ed F. Deprettere
Converting sequential iterative algorithms to recurrent equations for automatic design of systolic arrays.
ICASSP
(1988)
Jichun Bu
,
Ed F. Deprettere
A VLSI System Architecture for High-Speed Radiative Transfer 3D Image Synthesis.
Eurographics
(1987)