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One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs.

Gaël DeestTomofumi YukiSanjay V. RajopadhyeSteven Derrien
Published in: FPL (2017)
Keyphrases
  • trade off
  • hardware implementation
  • parallel computation
  • computational complexity
  • small size
  • implementation details
  • information retrieval
  • signal processing
  • efficient implementation
  • implementation issues