An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators.
Corentin FerryNicolas DerumignySteven DerrienSanjay V. RajopadhyePublished in: CoRR (2024)
Keyphrases
- compressed data
- bandwidth utilization
- field programmable gate array
- data compression
- single chip
- quality of service
- raw data
- compression ratio
- hardware implementation
- data cube
- compressed images
- lossless compression
- data structure
- high speed
- embedded systems
- low cost
- main memory
- reconstructed image
- image compression
- real time
- bitstream
- original data
- image quality
- databases
- bit rate
- response time
- query processing
- high quality