True hardware random number generation implemented in the 32-nm SOI POWER7+ processor.
John S. LibertyAdrian BarreraDavid W. BoerstlerThomas B. ChadwickScott R. CottierH. Peter HofsteeJulie A. RosserMarty L. TsaiPublished in: IBM J. Res. Dev. (2013)
Keyphrases
- silicon on insulator
- ibm power processor
- random number
- random number generator
- instruction set
- error resilience
- power management
- random numbers
- random number generators
- dynamic random access memory
- pseudorandom
- pseudo random number generators
- power consumption
- parallel processing
- high speed
- cmos technology
- memory subsystem
- ibm zenterprise
- multithreading
- single chip
- high end
- computational power
- low cost
- digital signal processor
- real time