Timed circuit verification using TEL structures.

Wendy Belluomini Chris J. Myers H. Peter Hofstee

Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2001)

Keyphrases

petri net
high speed
model checking
neural network
formal verification
database
face verification
digital circuits
low cost
technology enhanced learning
timed automata