Hua-Yu Chang

Publication Activity (10 Years)

Years Active: 2009-2022
Publications (10 Years): 5

Top Topics

Phase Congruency

Feature Detection

Recent Developments

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

IBM J. Res. Dev.

Publications

Wen-Hao Liu, Bing Chen, Hua-Yu Chang, Gary Lin, Zi-Shen Lin
Challenges for Automating Package Routing. ISPD (2022)
Hua-Yu Chang, Iris Hui-Ru Jiang
Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement. ISPD (2019)
Iris Hui-Ru Jiang, Hua-Yu Chang
Recent Research and Challenges in Multiple Patterning Layout Decomposition. ISVLSI (2018)
Iris Hui-Ru Jiang, Hua-Yu Chang
Multiple Patterning Layout Decomposition Considering Complex Coloring Rules and Density Balancing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (12) (2017)
Hua-Yu Chang, Iris Hui-Ru Jiang
Multiple patterning layout decomposition considering complex coloring rules. DAC (2016)
Hua-Yu Chang, Iris Hui-Ru Jiang, H. Peter Hofstee, Damir A. Jamsek, Gi-Joon Nam
Feature detection for image analytics via FPGA acceleration. IBM J. Res. Dev. 59 (2/3) (2015)
Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
Functional ECO Using Metal-Configurable Gate-Array Spare Cells. DAC (2014)
Iris Hui-Ru Jiang, Gi-Joon Nam, Hua-Yu Chang, Sani R. Nassif, Jerry Hayes
Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations. ICCAD (2014)
Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
ECO Optimization Using Metal-Configurable Gate-Array Spare Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (11) (2013)
Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (12) (2012)
Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
Timing ECO optimization using metal-configurable gate-array spare cells. DAC (2012)
Iris Hui-Ru Jiang, Hua-Yu Chang
ECOS: Stable Matching Based Metal-Only ECO Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 20 (3) (2012)
Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang
WiT: Optimal Wiring Topology for Electromigration Avoidance. IEEE Trans. Very Large Scale Integr. Syst. 20 (4) (2012)
Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
Timing ECO optimization via Bézier curve smoothing and fixability identification. ICCAD (2011)
Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang
Simultaneous functional and timing ECO. DAC (2011)
Iris Hui-Ru Jiang, Hua-Yu Chang
Live Demo: ECOS 1.0: A metal-only ECO synthesizer. ISCAS (2010)
Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang
Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles. ISPD (2010)
Iris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, Huang-Bi Hung
Matching-based minimum-cost spare cell selection for design changes. DAC (2009)