Martti Forsell

Publication Activity (10 Years)

Years Active: 1996-2023
Publications (10 Years): 14

Top Topics

Parallel Algorithm

Hardware And Software

Top Venues

IPDPS Workshops

Microprocess. Microsystems

Publications

Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff
Preliminary Performance and Memory Access Scalability Study of Thick Control Flow Processors. NorCAS (2023)
Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff
Realizing multioperations and multiprefixes in Thick Control Flow processors. Microprocess. Microsystems 98 (2023)
Martti Forsell, Sara Nikula, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff
Performance and programmability comparison of the thick control flow architecture and current multicore processors. J. Supercomput. 78 (3) (2022)
Martti Forsell, Jussi Roivainen, Jesper Larsson Träff
Optimizing Memory Access in TCF Processors with Compute-Update Operations. IPDPS Workshops (2020)
Mikko Uitto, Martti Forsell
Towards Energy-Efficient Adaptive Mpeg-Dash Streaming Using Hevc. ICME Workshops (2018)
Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff
Implementation of Multioperations in Thick Control Flow Processors. IPDPS Workshops (2018)
Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff
Supporting concurrent memory access in TCF processor architectures. Microprocess. Microsystems 63 (2018)
Martti Forsell, Jussi Roivainen, Ville Leppänen
REPLICA MBTAC: multithreaded dual-mode processor. J. Supercomput. 74 (5) (2018)
Jari-Matti Mäkelä, Martti Forsell, Ville Leppänen
Towards a Language Framework for Thick Control Flows. IPDPS Workshops (2017)
Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff
Supporting concurrent memory access in TCF-aware processor architectures. NORCAS (2017)
Martti Forsell, Jussi Roivainen, Ville Leppänen
The REPLICA on-chip network. NORCAS (2016)
Jari-Matti Mäkelä, Martti Forsell, Ville Leppänen
Compiler assisted dynamic allocation of finite hardware acceleration resources for parallel tasks. CompSysTech (2016)
Mohammadhassan Safavi, Saeed Bastani, Zhi Zhang, Martti Forsell, Olli Mämmelä, Björn Landfeldt
A study on energy used to deliver H.264/AVC and H.265/HEVC video content. CAMAD (2016)
Martti Forsell, Jussi Roivainen, Ville Leppänen
Outline of a Thick Control Flow Architecture. SBAC-PAD (Workshops) (2016)
Martti Forsell, Ville Leppänen, Martti Penttonen
Cost of Bandwidth-Optimized Sparse Mesh Layouts. PaCT (2015)
Martti Forsell, Erik Hansson, Christoph W. Kessler, Jari-Matti Mäkelä, Ville Leppänen
NUMA Computing with Hardware and Software Co-Support on Configurable Emulated Shared Memory Architectures. Int. J. Netw. Comput. 4 (1) (2014)
Thomas Canhao Xu, Ville Leppänen, Martti Forsell
Exploration of a Heterogeneous Concentrated-Sparse On-Chip Interconnect for Energy Efficient Multicore Architecture. CIT (2014)
Erik Hansson, Erik Alnervik, Christoph W. Keßler, Martti Forsell
A Quantitative Comparison of PRAM based Emulated Shared Memory Architectures to Current Multicore CPUs and GPUs. ARCS Workshops (2014)
Martti Forsell, Jussi Roivainen
REPLICA T7-16-128 - A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor. ACSSC (2014)
Martti Forsell, Jussi Roivainen, Ville Leppänen
Prototyping the MBTAC Processor for the REPLICA CMP. IPDPS Workshops (2014)
Thomas Canhao Xu, Ville Leppänen, Martti Forsell
DSNOC: A Hybrid Dense-Sparse Network-on-Chip Architecture for Efficient Scalable Computing. DASC (2013)
Martti Forsell, Ville Leppänen
An Extended PRAM-NUMA Model of Computation for TCF Programming. Int. J. Netw. Comput. 3 (1) (2013)
Jari-Matti Mäkelä, Ville Leppänen, Martti Forsell
Towards a parallel debugging framework for the massively multi-threaded, step-synchronous REPLICA architecture. CompSysTech (2013)
Martti Forsell, Erik Hansson, Christoph W. Kessler, Jari-Matti Mäkelä, Ville Leppänen
Hardware and Software Support for NUMA Computing on Configurable Emulated Shared Memory Architectures. IPDPS Workshops (2013)
Jari-Matti Mäkelä, Erik Hansson, Daniel Åkesson, Martti Forsell, Christoph W. Kessler, Ville Leppänen
Design of the Language Replica for Hybrid PRAM-NUMA Many-core Architectures. ISPA (2012)
Martti Forsell, Ville Leppänen
An Extended PRAM-NUMA Model of Computation for TCF Programming. IPDPS Workshops (2012)
Martti Forsell, Mikko Hiivala
Multi-core Portability Abstraction. IPDPS Workshops (2012)
Jari-Matti Mäkelä, Ville Leppänen, Martti Forsell
Preliminary analysis of feasible benchmark problems for the hydrid PRAM/NUMA REPLICA architecture. CompSysTech (2012)
Martti Forsell, Ville Leppänen
A moving threads processor architecture MTPA. J. Supercomput. 57 (1) (2011)
Martti Forsell
Performance comparison of some shared memory organizations for 2D mesh-like NOCs. Microprocess. Microsystems 35 (2) (2011)
Martti Forsell, Ville Leppänen, Martti Penttonen
Cost of Sparse Mesh Layouts Supporting Throughput Computing. DSD (2011)
Ville Leppänen, Martti Penttonen, Martti Forsell
A layout for sparse cube-connected-cycles network. CompSysTech (2011)
Jari-Matti Mäkelä, Ville Leppänen, Martti Forsell
RISC-based moving threads multicore architecture. CompSysTech (2011)
Martti Forsell
A PRAM-NUMA Model of Computation for Addressing Low-TLP Workloads. Int. J. Netw. Comput. 1 (1) (2011)
Martti Forsell, Jesper Larsson Träff
HPPC 2010: 5th Workshop on Highly Parallel Processing on a Chip. Euro-Par Workshops (1) (2010)
Martti Forsell, Jesper Larsson Träff
HPPC 2010: Forth Workshop on Highly Parallel Processing on a Chip. Euro-Par Workshops (2010)
Ville Leppänen, Martti Penttonen, Martti Forsell
Layouts for Sparse Networks Supporting Throughput Computing. PDPTA (2010)
Martti Forsell
A PRAM-NUMA model of computation for addressing low-TLP workloads. IPDPS Workshops (2010)
Martti Forsell
On the Performance and Cost of Some PRAM Models on CMP Hardware. Int. J. Found. Comput. Sci. 21 (3) (2010)
Martti Forsell, Ville Leppänen
Supporting Concurrent Memory Access and Multioperations in Moving Threads CMPs. PDPTA (2010)
Jani Paakkulainen, Jari-Matti Mäkelä, Ville Leppänen, Martti Forsell
Outline of RISC-based core for multiprocessor on chip architecture supporting moving threads. CompSysTech (2009)
Martti Forsell
Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions. NOCS (2009)
Martti Forsell, Ville Leppänen
MTPA - A Processor Architecture for MP-SOCs Employing the Moving Threads Paradigm. PDPTA (2009)
Martti Forsell, Jesper Larsson Träff
HPPC 2009: 3rd Workshop on Highly Parallel Processing on a Chip. Euro-Par Workshops (2009)
Martti Forsell, H. Peter Hofstee, Ahmed Jerraya, Chris R. Jesshope, Uzi Vishkin, Jesper Larsson Träff
HPPC 2009 Panel: Are Many-Core Computer Vendors on Track? Euro-Par Workshops (2009)
Martti Forsell, Jussi Roivainen
Performance, Area and Power Trade-Offs in Mesh-based Emulated Shared Memory CMP Architectures. PDPTA (2008)
Martti Forsell, Jesper Larsson Träff
Second Workshop on Highly Parallel Processing on a Chip (HPPC 2008). Euro-Par Workshops (2008)
Martti Forsell
On the performance and cost of some PRAM models on CMP hardware. IPDPS (2008)
Martti Forsell, Ville Leppänen
Moving Threads: A Non-Conventional Approach for Mapping Computation to MP-SOC. PDPTA (2007)
Martti Forsell, Jesper Larsson Träff
HPPC 2007: Workshop on Highly Parallel Processing on a Chip. Euro-Par Workshops (2007)
Martti Forsell
Realizing Multioperations for Step Cached MP-SOCs. SoC (2006)
Martti Forsell
Realising constant time parallel algorithms with active memory modules. Int. J. Electron. Bus. 3 (3/4) (2005)
Martti Forsell
ParLe - A Parallel Computing Learning Set for MPSOCs/NOCs. SoC (2005)
Martti Forsell
Ec - a compiler for the e-language [NOC applications]. SoC (2004)
Martti Forsell
Efficient barrier synchronization mechanism for emulated shared memory NOCs. SoC (2004)
Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar
Extending Platform-Based Design to Network on Chip Systems. VLSI Design (2003)
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani
A Network on Chip Architecture and Design Methodology. ISVLSI (2002)
Martti Forsell
A Scalable High-Performance Computing Solution for Networks on Chips. IEEE Micro 22 (5) (2002)
Eugene I. Ageenko, Martti Forsell, Pasi Fränti
Context-based compression of binary images in parallel. Softw. Pract. Exp. 32 (13) (2002)
Juha-Pekka Soininen, Jari Kreku, Yang Qu, Martti Forsell
Fast processor core selection for WLAN modem using mappability estimation. CODES (2002)
Martti Forsell
Architectural differences of efficient sequential and parallel computers. J. Syst. Archit. 47 (13) (2002)
Martti Forsell
MTAC - A Multithreaded VLIW Architecture for PRAM Simulation. J. Univers. Comput. Sci. 3 (9) (1997)
Martti Forsell
Minimal pipeline architecture - an alternative to superscalar architecture. Microprocess. Microsystems 20 (5) (1996)
Martti Forsell, Martti Penttonen, Ville Leppänen
Efficient Two-Level Mesh based Simulation of PRAMs. ISPAN (1996)