Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process.

Joachim Fenkes Tobias Gemmeke Jens Leenstra

Published in: J. Low Power Electron. (2007)

Keyphrases

low power
high speed
cmos technology
power consumption
logic circuits
power reduction
low cost
vlsi circuits
nm technology
power dissipation
delay insensitive
gate array
low power consumption
silicon on insulator
low voltage
high power
vlsi architecture
computational complexity