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A 1.8-GHz instruction window buffer for an out-of-order microprocessor core.

Jens LeenstraJürgen PilleAntje MüllerWolfram M. SauerRolf SautterDieter F. Wendel
Published in: IEEE J. Solid State Circuits (2001)
Keyphrases
  • high speed
  • instruction set
  • real time
  • data sets
  • neural network
  • multiresolution
  • online learning
  • learning outcomes
  • steady state
  • circuit design