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A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS.

Hazar YuekselMatthias BraendliAndreas BurgGiovanni CherubiniRoy D. CideciyanPier Andrea FranceseSimeon FurrerMarcel A. KosselLukas KullDanny LuuChristian MenolfiThomas MorfThomas Toifl
Published in: ESSCIRC (2016)
Keyphrases
  • high speed
  • state space
  • power consumption
  • data sets
  • neural network
  • low cost
  • multiscale
  • object recognition
  • detection algorithm
  • sliding window