Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS.
Lukas KullJan PlívaThomas ToiflMartin L. SchmatzPier Andrea FranceseChristian MenolfiMatthias BraendliMarcel A. KosselThomas MorfToke Meyer AndersenYusuf LeblebiciPublished in: IEEE J. Solid State Circuits (2016)
Keyphrases
- low power
- cmos technology
- power consumption
- low cost
- high speed
- low voltage
- ultra low power
- single chip
- energy dissipation
- vlsi architecture
- nm technology
- vlsi circuits
- high power
- power dissipation
- image sensor
- signal processor
- logic circuits
- mixed signal
- digital signal processing
- wireless transmission
- delay insensitive
- low power consumption
- video streaming
- power reduction
- real time
- gate array
- video sequences