A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.
Gautam R. GangasaniChun-Ming HsuJohn F. BulzacchelliTroy J. BeukemaWilliam KellyHui H. XuDavid FreitasAndrea PratiDaniele GardelliniRobert ReutemannGiovanni CervelliJuergen HertleMatthew BaecherJon GarlettPier Andrea FranceseJohn F. EwenDavid HansonDaniel W. StoraskaMounir MeghelliPublished in: IEEE J. Solid State Circuits (2014)
Keyphrases
- low latency
- silicon on insulator
- cmos technology
- high speed
- low power
- high bandwidth
- low voltage
- real time
- mixed signal
- highly efficient
- high throughput
- parallel processing
- image sensor
- power dissipation
- phase locked loop
- power consumption
- low cost
- stream processing
- data acquisition
- ibm power processor
- embedded dram
- multimedia