A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI.
Marcel A. KosselChristian MenolfiThomas ToiflPier Andrea FranceseMatthias BraendliThomas MorfLukas KullToke Meyer AndersenHazar YuekselPublished in: ESSCIRC (2014)
Keyphrases
- bitstream
- rate control
- bit rate
- silicon on insulator
- video quality
- rate distortion
- macroblock
- video coding
- visual quality
- video streaming
- rate control scheme
- subband
- high speed
- cmos technology
- video transmission
- rate control algorithm
- inter frame
- motion vectors
- image quality
- compressed video
- computational complexity
- frame rate
- metal oxide
- transmission electron microscopy
- error propagation
- power consumption
- video codec
- ibm power processor
- power dissipation
- random access memory
- nm technology
- distributed video coding
- high resolution