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A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI.

Marcel A. KosselChristian MenolfiThomas ToiflPier Andrea FranceseMatthias BraendliThomas MorfLukas KullToke Meyer AndersenHazar Yueksel
Published in: ESSCIRC (2014)
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