28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET.
Lukas KullDanny LuuChristian MenolfiMatthias BraendliPier Andrea FranceseThomas MorfMarcel A. KosselHazar YuekselAlessandro CevreroIlter ÖzkayaThomas ToiflPublished in: ISSCC (2017)
Keyphrases
- analog to digital converter
- cmos technology
- silicon on insulator
- high speed
- camera calibration
- sar images
- metal oxide semiconductor
- synthetic aperture radar
- low cost
- single chip
- power consumption
- automatic target recognition
- power supply
- image sensor
- low voltage
- computer vision
- data flow
- foreground objects
- linear array
- delay insensitive
- analog vlsi
- camera parameters
- image reconstruction
- moving objects