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10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme.
Mark A. Ferriss
Bodhisatwa Sadhu
Alexander V. Rylyakov
Herschel A. Ainspan
Daniel J. Friedman
Published in:
ISSCC (2015)
Keyphrases
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silicon on insulator
noise cancellation
input output
high speed
adaptive algorithms
power consumption
adaptive filter
restoration algorithm
noise reduction
cmos technology
artificial neural networks
higher order
image quality
low power