Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS".
Zeynep Toprak DenizJonathan E. ProeselJohn F. BulzacchelliHerschel A. AinspanTimothy O. DicksonMichael P. BeakesMounir MeghelliPublished in: IEEE J. Solid State Circuits (2020)
Keyphrases
- power supply
- low cost
- high speed
- metal oxide semiconductor
- cmos technology
- silicon on insulator
- low power
- nm technology
- floating gate
- power reduction
- power consumption
- reconfigurable architecture
- general purpose
- low voltage
- multi objective evolutionary
- hardware implementation
- analog vlsi
- real time
- single chip
- integrated circuit
- communication systems
- video camera
- digital camera
- parallel processing
- transmission scheme
- fine grain
- delay insensitive
- received signal
- image sensor
- digital signal
- transmission electron microscopy
- hd video
- signal to noise ratio
- field programmable gate array