Debajit Bhattacharya

Publication Activity (10 Years)

Years Active: 2013-2017
Publications (10 Years): 4

Top Topics

Design Considerations

Magnetic Recording

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Multi Scale Comput. Syst.

Publications

Debajit Bhattacharya, Niraj K. Jha
Analytical Modeling of the SMART NoC. IEEE Trans. Multi Scale Comput. Syst. 3 (4) (2017)
Debajit Bhattacharya, Niraj K. Jha
Ultra-High Density Monolithic 3-D FinFET SRAM With Enhanced Read Stability. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2016)
Debajit Bhattacharya, Niraj K. Jha
TCAD-Assisted Capacitance Extraction of FinFET SRAM and Logic Arrays. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha
Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism. VLSI Design (2016)
Debajit Bhattacharya, Ajay N. Bhoj, Niraj K. Jha
Design of Efficient Content Addressable Memories in High-Performance FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. 23 (5) (2015)
Debajit Bhattacharya, Rajiv V. Joshi, Herschel A. Ainspan, Ninad D. Sathaye, Mohit Bajaj, Suresh Gundapaneni, Niraj K. Jha
TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology. CICC (2014)
Debajit Bhattacharya, Ashis Maity, Amit Patra
Design and Implementation of a High-Speed, Power-Efficient, Modified Hybrid-Mode Sense Amplifier for SRAM Applications. VLSI Design (2013)