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Sourindra Chaudhuri
Publication Activity (10 Years)
Years Active: 2011-2016
Publications (10 Years): 1
Top Topics
Logic Circuits
Response Surface Methodology
Optimization Model
Significantly Higher
Top Venues
VLSI Design
ACM J. Emerg. Technol. Comput. Syst.
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Publications
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Sourindra Chaudhuri
,
Ajay N. Bhoj
,
Debajit Bhattacharya
,
Niraj K. Jha
Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism.
VLSI Design
(2016)
Sourindra Chaudhuri
,
Niraj K. Jha
FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage.
VLSI Design
(2014)
Sourindra Chaudhuri
,
Niraj K. Jha
3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations.
ACM J. Emerg. Technol. Comput. Syst.
10 (3) (2014)
Sourindra Chaudhuri
,
Prateek Mishra
,
Niraj K. Jha
Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology.
VLSI Design
(2012)
Sourindra Chaudhuri
,
Niraj K. Jha
3D vs. 2D analysis of FinFET logic gates under process variations.
ICCD
(2011)