Ajay N. Bhoj

Publication Activity (10 Years)

Years Active: 2009-2016
Publications (10 Years): 1

Top Topics

Design Methodology

Content Addressable

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha
Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism. VLSI Design (2016)
Debajit Bhattacharya, Ajay N. Bhoj, Niraj K. Jha
Design of Efficient Content Addressable Memories in High-Performance FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. 23 (5) (2015)
Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj, Ajay N. Bhoj, Matthew M. Ziegler, Phil Oldiges, Pranita Kerber, Robert Wong, Terence Hook, Sudesh Saroop, Carl Radens, Chun-Chen Yeh
Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction. IEEE Trans. Very Large Scale Integr. Syst. 23 (3) (2015)
Ajay N. Bhoj, Niraj K. Jha
Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Ajay N. Bhoj, Niraj K. Jha
Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. 21 (11) (2013)
Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha
Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (1) (2013)
Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha
3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits. IEEE Trans. Very Large Scale Integr. Syst. 21 (11) (2013)
Ajay N. Bhoj, Niraj K. Jha
Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology. ISQED (2011)
Ajay N. Bhoj, Niraj K. Jha
Gated-diode FinFET DRAMs: Device and circuit design-considerations. ACM J. Emerg. Technol. Comput. Syst. 6 (4) (2010)
Prateek Mishra, Ajay N. Bhoj, Niraj K. Jha
Die-level leakage power analysis of FinFET circuits considering process variations. ISQED (2010)
Muzaffer O. Simsir, Ajay N. Bhoj, Niraj K. Jha
Fault modeling for FinFET circuits. NANOARCH (2010)
Ajay N. Bhoj, Niraj K. Jha
Pragmatic design of gated-diode FinFET DRAMs. ICCD (2009)