A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS.
Byungsub KimYong LiuTimothy O. DicksonJohn F. BulzacchelliDaniel J. FriedmanPublished in: IEEE J. Solid State Circuits (2009)
Keyphrases
- low power
- cmos technology
- high speed
- decision feedback
- nm technology
- power consumption
- low cost
- single chip
- low voltage
- mixed signal
- image sensor
- vlsi circuits
- error propagation
- power reduction
- power dissipation
- multipath
- vlsi architecture
- digital signal processing
- silicon on insulator
- ultra low power
- low power consumption
- logic circuits
- real time
- power saving
- power management
- gate array
- delay insensitive
- image processing algorithms
- hardware and software
- file system
- image processing