Login / Signup
Joseph Natonio
Publication Activity (10 Years)
Years Active: 2000-2012
Publications (10 Years): 0
Top Venues
IEEE J. Solid State Circuits
</>
Publications
</>
Gautam R. Gangasani
,
Chun-Ming Hsu
,
John F. Bulzacchelli
,
Sergey V. Rylov
,
Troy J. Beukema
,
David Freitas
,
William Kelly
,
Michael Shannon
,
Jieming Qi
,
Hui H. Xu
,
Joseph Natonio
,
Todd M. Rasmus
,
Jong-Ru Guo
,
Michael Wielgos
,
Jon Garlett
,
Michael Sorna
,
Mounir Meghelli
A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology.
IEEE J. Solid State Circuits
47 (8) (2012)
Gautam R. Gangasani
,
Chun-Ming Hsu
,
John F. Bulzacchelli
,
Sergey V. Rylov
,
Troy J. Beukema
,
David Freitas
,
William Kelly
,
Michael Shannon
,
Jieming Qi
,
Hui H. Xu
,
Joseph Natonio
,
Todd M. Rasmus
,
Jong-Ru Guo
,
Michael Wielgos
,
Jon Garlett
,
Michael Sorna
,
Mounir Meghelli
A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology.
CICC
(2011)
Ram Kelkar
,
Dave Flye
,
Anjali Malladi
,
Joseph Natonio
,
Chri Scoville
,
Ken Short
,
Pradeep Thiagarajan
A Low Jitter Programmable Frequency Synthesizer for 4.25Gbps Serial Link Applications.
SoCC
(2005)
Patrick H. Buffet
,
Joseph Natonio
,
Robert A. Proctor
,
Yu H. Sun
,
Gulsun Yasar
Methodology for I/O cell placement and checking in ASIC designs using area-array power grid.
CICC
(2000)