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A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology.

Gautam R. GangasaniChun-Ming HsuJohn F. BulzacchelliSergey V. RylovTroy J. BeukemaDavid FreitasWilliam KellyMichael ShannonJieming QiHui H. XuJoseph NatonioTodd M. RasmusJong-Ru GuoMichael WielgosJon GarlettMichael SornaMounir Meghelli
Published in: CICC (2011)
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