Tim Piessens

Publication Activity (10 Years)

Years Active: 2002-2017
Publications (10 Years): 4

Top Topics

Vlsi Architecture

Charge Coupled Device

Top Venues

IEEE J. Solid State Circuits

Publications

Tim Piessens, Seung-Tak Ryu, Chih-Ming Hung, Alyosha C. Molnar, Mounir Meghelli
Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 52 (12) (2017)
Tim Piessens, Vadim Ivanov, Axel Thomsen
Session 5 overview: Analog techniques. ISSCC (2017)
Florian De Roose, Kris Myny, Soeren Steudel, Myriam Willigems, Steve Smout, Tim Piessens, Jan Genoe, Wim Dehaene
16.5 A flexible thin-film pixel array with a charge-to-current gain of 59µA/pC and 0.33% nonlinearity and a cost effective readout circuit for large-area X-ray imaging. ISSCC (2016)
Marco Berkhout, Tim Piessens
Session 5 overview: Analog techniques. ISSCC (2016)
Bert Serneels, Eldert Geukens, Bram De Muer, Tim Piessens
A 1.5W 10V-output Class-D amplifier using a boosted supply from a single 3.3V input in standard 1.8V/3.3V 0.18μm CMOS. ISSCC (2012)
Yashodhan Moghe, Torsten Lehmann, Tim Piessens
Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 μ m HV-CMOS Technology. IEEE J. Solid State Circuits 46 (2) (2011)
Bert Serneels, Tim Piessens, Michiel Steyaert, Wim Dehaene
A high-voltage output driver in a 2.5-V 0.25-/spl mu/m CMOS technology. IEEE J. Solid State Circuits 40 (3) (2005)
Tim Piessens, Michiel Steyaert
Behavioral analysis of self-oscillating class D line drivers. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2005)
Tim Piessens, Michiel Steyaert
Highly efficient xDSL line drivers in 0.35-μm CMOS using a self-oscillating power amplifier. IEEE J. Solid State Circuits 38 (1) (2003)
Tim Piessens, Michiel Steyaert
Oscillator pulling and synchronisation issues in self-oscillating class D power amplifiers. ESSCIRC (2003)
Tim Piessens, Michiel Steyaert
A central office combined ADSL-VDSL line driver solution in .35μm CMOS. CICC (2002)