A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.
Yong LiuPing-Hsuan HsiehSeongwon KimJae-sun SeoRobert K. MontoyeLeland ChangJosé A. TiernoDaniel J. FriedmanPublished in: ISSCC (2013)
Keyphrases
- silicon on insulator
- low power
- cmos technology
- high speed
- ibm power processor
- power consumption
- power management
- low cost
- single chip
- low voltage
- mixed signal
- power dissipation
- error resilience
- vlsi architecture
- digital signal processing
- vlsi circuits
- real time
- image sensor
- instruction set
- charge coupled devices
- logic circuits
- energy efficiency
- low power consumption
- file system
- power saving
- data center
- main memory