Sandip Tiwari

Publication Activity (10 Years)

Years Active: 2004-2017
Publications (10 Years): 2

Top Topics

Computational Power

Neural Computation

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

ACM J. Emerg. Technol. Comput. Syst.

Publications

Sandip Tiwari, Damien Querlioz
On the Physical Underpinnings of the Unusual Effectiveness of Probabilistic and Neural Computation. ICRC (2017)
Sandip Tiwari
Implications of Scales in Processing of Information. Proc. IEEE 103 (8) (2015)
Jaeyoon Kim, Sandip Tiwari
Inexact computing using probabilistic circuits: Ultra low-power digital processing. ACM J. Emerg. Technol. Comput. Syst. 10 (2) (2014)
Sandip Tiwari
Nanostructure devices for logic and memory and beyond. ESSDERC (2012)
Jaeyoon Kim, Paul Michael Solomon, Sandip Tiwari
Adaptive Circuit Design Using Independently Biased Back-Gated Double-Gate MOSFETS. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2012)
Jaeyoon Kim, Sandip Tiwari
Inexact computing for ultra low-power nanometer digital circuit design. NANOARCH (2011)
Sang-Hyeon Lee, Moonkyung Mark Kim, Byung-ki Cheong, Jooyeon Kim, Jo-Won Lee, Sandip Tiwari
A Single Element Phase Change Memory. IEICE Trans. Electron. (5) (2011)
Sandip Tiwari
Nanoelectronics Device Technologies: CMOS, Beyond and the Mysterious Case of Ockham's Razor. VLSI Design (2007)
Christianto C. Liu, Sandip Tiwari
Performance advantages of 3-D digital integrated circuits in a mixed SOI and bulk CMOS design space. IEEE Trans. Circuits Syst. II Express Briefs (3) (2006)
Uygar Avci, Sandip Tiwari
A novel compact circuit for 4-PAM energy-efficient high speed interconnect data transmission and reception. Microelectron. J. 36 (1) (2005)
Christianto C. Liu, Jeng-Huei Chen, Rajit Manohar, Sandip Tiwari
Mapping system-on-chip designs from 2-D to 3-D ICs. ISCAS (3) (2005)
Christianto C. Liu, Ilya Ganusov, Martin Burtscher, Sandip Tiwari
Bridging the Processor-Memory Performance Gapwith 3D IC Technology. IEEE Des. Test Comput. 22 (6) (2005)
Arvind Kumar, Sandip Tiwari
A power-performance adaptive low voltage analog circuit design using independently controlled double gate CMOS technology. ISCAS (1) (2004)
Arvind Kumar, Sandip Tiwari
Testing and Defect Tolerance: A Rent's Rule Based Analysis and Implications on Nanoelectronics. DFT (2004)
Arvind Kumar, Sandip Tiwari
Defect tolerance for nanocomputer architecture. SLIP (2004)